Pipelined MIPS Processor

Capstone project for Computer Organization. Created a pipelined MIPS processor in Verilog. Components included Instruction memory, Registers, ALU, Instruction Memory, Datapath & Control and Hazard Detection Unit.

Pipelined MIPS Github

Five stage pipeline

1. Instruction Fetch

2. Instruction Decode

3. Execute

4. Memory Fetch/Write

5. Memory Write-back